logic function – Global Homework Experts

ECE3421 Lab 6
In this lab, you will design the logic function F = A(B+C)+D using dynamic
CMOS implementation. You may re-use the NMOS part from Lab 5. Finish
schematic and layout.
(a) Keep A, B, and C at zero, and D has a low-to-high transition in the middle of
the evaluation phase. Simulate and obtain output waveforms.
(b) Keep A, B, and C at zero, and D has a high-to-low transition in the middle of
the evaluation phase. Simulate and obtain output waveforms.
(c) Explain whether the outputs of the above two cases generate the correct logic
values or not.

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